Failure analysis for Yield Learning³

        A schematic view of a VLSI manufacturing line is shown in figure 1. The structure of a manufacturing line was perspective of a linear flow of wafers from input to the point where IC’s are ready to be shipped. From a yield learning point of view, however, one has also to factor in the role of failure analysis as shown in Figure 1. After the probe and final testing stages, wafers with defective dies and packaged defective IC’s are sampled for failure analysis. After the causes of observed failures are detected and diagnosed, certain corrective actions need to be taken. Corrective actions are taken so as to remove or reduce causes of yield loss in the fabrication stage.

        One can further simplify the view of a manufacturing line as shown in Figure 2. since such a view is sufficient to illustrate the main attributes of yield learning Here, the manufacturing line is shown to consist of three phases: wafer fabrication, probe testing and failure analysis. Wafers are processed in a sequence of steps defined by the process recipe. At each step, a unique piece of equipment is used, and a specific layer of the IC defined. Disturbances can be introduced at each of these steps resulting in a less than ideal environment for processing the wafers.

  Figure³ 1.Structure of Manufacturing line -yield learning perspective

        After completing the fabrication process, every die on each wafer is subjected to probe testing to detect faults. The tested wafers are diced and the punctionally acceptable die are packaged and tested further. A fraction of the tested wafers are selected to perform failure analysis. During failure analysis a fraction of the defective die on the sampled wafers are carefully analyzed in order to detect the dominant cause of failures. Based on this analysis, corrective actions are taken on the piece of fabrication equipment found responsible for the observed failures.

Figure³ 2.     Simplified schematic of a manufacturing line

        From the figure 2., the corrective actions are given by the failure analysis phase to the wafer fabrication phase. Hence, the failure analysis phase has significant control in the yield learning rate of the wafer fabrication process. The failure analysis has 2 kinds of activities which monitor the quality of the wafer in-line monitoring of partially fabricated wafers and off-line defect diagnosis of completely fabricated wafers or packaged ICs.

        In-line monitoring gives an idea of the number of defects in a wafer lot. This information as such does not implicate anything but this provides important information for the defect diagnosis (off-line) phase. There is a possibility that a correlation of all the data gathered on a particular wafer with the results of testing can be made and a list of likely candidates for particles/defects for each defective die on the wafer can be generated. One can create trend charts for particles for each piece of equipment and use these to guide the defect diagnosis process also.

        Diagnosis of defects in packaged ICs is essentially similar to that of wafers and the important differences will be pointed out where appropriate. A single cycle of defect diagnosis begins with a sample to be analyzed and ends with identification of the equipment (or any other source) responsible for the observed defect.

        Research in the area of particle monitoring and especially defect diagnosis has been limited to finding better mechanisms to perform the analyses. Currently no models or methods have been investigated to judge the efficiency and accuracy of these processes in the context of yield learning. The rate of yield learning depends to a great extent on the rate of correct feedback to the wafer fabrication process so that problems can be corrected. It also depends on the change in particle/defect characteristics as a result of corrective actions which is dealt with in the next section.