Module #2 - Test Economics

The goal of test economics is to minimize the cost of discarding good product and the cost of shipping bad product.  The basic testing questions that we wish to gain insight into in this lecture are:

• When should a system be tested?  (at what point(s) in the manufacturing process?)
• How much testing should be done?  (how thorough should the testing be?)
• What steps should I take to make the system more testable?

NOTE, the following Lectures, Calculators and Problems are under development and may be non-existent, incomplete, or changed without notice.

Relevant Links and References

J. Turino, "Test Economics in the 21st Century," IEEE Design & Test of Computers, Vol. 14, No. 3, July - September 1997.

B. Davis, "The Economics of Automatic Testing," Electrochemical Publications.

A. Crouch, "Design-For-Test For Digital IC's and Embedded Core Systems," Prentice Hall, 2000.

T. Trichy, P. Sandborn, R. Raghavan, and S. Sahasrabudhe, “A New Test/Diagnosis/Rework Model for Use in Technical Cost Modeling of Electronic Systems Assembly,” in Proceedings of the International Test Conference, pp. 1108-1117, November 2001.

"Proceedings of the first International Workshop on the Economics of Design, Manufacture and Test," Ellis Horwood, 1992.

"Proceedings of the second International Workshop on the Economics of Design, Manufacture and Test," Kluwer Academic Publishers, 1993.

"Proceedings of the third International Workshop on the Economics of Design, Manufacture and Test," IEEE Computer Society Press, 1994.

C. Dislis, J. H. Dick, I. D. Dear, and A. P. Ambler, Test Economics and Design for Testability, Ellis Horwood, 1995.

P. Sandborn and H. Moreno, Conceptual Design of Multichip Modules and Systems, Kluwer Academic Publishers, 1994.

T. W. Williams, and N. C. Brown, "Defect Level as a Function of Fault Coverage", IEEE Transactions on Computers, pp. 987-988, December 1981.

M. Abadir, A. Parikh, L. Bal, P. Sandborn, and C. Murphy, "High Level Test Economics Advisor", Journal of Electronic Testing: Theory and Applications, vol. 5, pp. 195-206, May 1994.

C. Dislis, J. H. Dick, I.D. Dear, I.N. Azu, and A.P. Ambler, "Economics Modeling for the Determination of Test Strategies for Complex VLSI Boards", Proceedings of the 1993 International Test Conference, pp. 210-217.